The present invention relates to solid-state imaging device and, more particularly, is directed to a solid-state imager having FETs (field effect transistors) and load capacitors.
As the demand for high resolution solid-state imaging devices increases, there have been developed so far internal amplifier type solid-state imaging devices for amplifying light signal charges at every pixel. As the internal amplifier type solid-state imaging device, there are mainly various kinds of imaging device structures, such as a static induction transistor (SIT), an amplifying type MOS imager (AMI), a charge modulation device (CMD) and a BASIS (base-stored image sensor) using a bipolar transistor as a pixel.
An amplifier type solid-state imaging device called a WAM (well control amplified MOS (metal oxide semiconductor) imager) is known as one of such internal amplifier type solid-state imaging devices. In this amplifier type solid-state imaging device, holes (signal charges) obtained by photoelectric conversion are accumulated in a P-type potential well of an N-channel MOS transistor (pixel MOS transistor) and the change of a channel current based on the change of potential in the P-type potential well (i.e., change of potential in the back gate) is output as a pixel signal.
FIG. 1 of the accompanying drawings shows an example of an amplifier type solid-state imaging device 11. As shown in FIG. 1, there are arrayed pixel MOS transistors [unit pixels (cells)] 1 in a matrix fashion. The gate of each pixel MOS transistor 1 is connected to a vertical scanning line 3 scanned by a vertical scanning circuit 2 formed of a shift register or the like. The drain of each pixel MOS transistor 1 is connected to a power supply line (line to which a voltage VDD is supplied) 4 and the source thereof is connected to a vertical signal line 5.
Each of the signal vertical signal lines 5 is connected with a load MOS transistor 6 whose gate has a bias voltage VB applied thereto. A sample and hold circuit 7 for sampling and holding a pixel signal also is connected to each vertical signal line 5. In FIG. 1, reference numeral 8 depicts a horizontal scanning circuit. The horizontal scanning circuit 8 outputs a pixel signal from the sample and hold circuit 7 through a horizontal output signal line 10 by sequentially supplying a scanning signal to the gate of each of horizontal MOS switches 9.
In the amplifier type solid-state imaging device 11, as shown in the schematic diagram of FIG. 1 and a diagram of an equivalent circuit of FIG. 2 realized when a pixel is scanned, the unit pixel, i.e. the pixel MOS transistor 1, is scanned by the vertical scanning circuit 2 through the vertical scanning line 3. Then, a signal obtained from a source-follower circuit formed of the pixel MOS transistor 1 and the load MOS transistor 6 connected to the vertical signal line 5 as a constant current source is sampled and held by the sample and hold circuit 7 and the horizontal MOS switches 9 connected to the horizontal scanning circuit 8 are sequentially energized to thereby output the signal of each pixel MOS transistor 1 through the horizontal 2 output signal line 10.
Specifically, the scanned pixel MOS transistor 1 and the load MOS transistor 6 operate as the source-follower circuit to output a source potential obtained under the condition that a current is constantly flowed in the pixel MOS transistor 1 via the sample and hold circuit 7 and the horizontal MOS switch 9. Therefore, it is possible to obtain a signal output of the solid-state imaging device by carrying out the above-mentioned operation at every horizontal scanning line while the vertical scanning line 3 for scanning the pixel MOS transistor 1 is being changed.
However, in the above-mentioned case, operation conditions of the pixel MOS transistor 1 disposed away from the load MOS transistor 6 and the pixel MOS transistor 1 disposed near the load MOS transistor 6 are changed by a distributed resistance with the result that sensitivity is deteriorated in the vertical direction.
If a constant current property of the load MOS transistor 6 operated as the constant current source is unsatisfactory, there is then the disadvantage that sensitivity of the solid-state imaging device is lowered. In other words, the load MOS transistor 6 operated as the constant current source is not an ideal constant current source. Therefore, if the source current of the pixel MOS transistor 1 is changed, then the constant current is fluctuated very slightly and a fluctuated amount of the constant current causes sensitivity to be lowered.
Moreover, since the constant current is always flowed when a signal voltage is read out from the pixel MOS transistor 1, an imaging device consumes much power.
Further, when the constant current of the load MOS transistor 6 is fluctuated, there is generated a vertical stripe-shaped fixed pattern noise (FPN) which is difficult to be removed by signal processing.
Furthermore, when a signal voltage is read out from the pixel MOS transistor 1, the constant current, i.e. a relatively large drain current is flowed, so that a mutual conductance gm of the pixel MOS transistor 1 is large. As a result, a random noise generated from the pixel MOS transistor 1 becomes large as compared with the mutual conductance gm.
In view of the aforesaid aspect, it is an object of the present invention to provide an amplifier type solid-state imaging device of a capacitor load operation system in which sensitivity can be made uniform, sensitivity can be increased, a power consumption can be reduced and a fixed pattern noise can be removed.
It is another object of the present invention to provide an amplifier type solid-state imaging device of a capacitor load operation system which can be made more reliable and in which an arrangement of a horizontal output circuit portion can be simplified.
It is a further object of the present invention to provide a solid-state imaging device of a capacitor load operation system in which a random noise of a pixel transistor can be reduced.
According to a first aspect of the present invention, there is provided a solid-state imaging device which is comprised of a plurality of pixel MOS transistors for storing signal charges generated by photoelectric conversion, each of the pixel MOS transistors composed of a gate electrode connected to a vertical scanning line, a drain connected to a voltage source and a source connected to a vertical signal line, a capacitor connected between the vertical signal line and a fixed potential, a reset device for resetting a potential of the capacitor to set a reset potential, and a switch for controlling a connection between one of the pixel MOS transistors and the capacitor so that a potential of the capacitor has the same potential as a channel potential of the pixel MOS transistor selected.
According to a second aspect of the present invention, there is provided a solid-state imaging device which is comprised of a plurality of pixel bipolar transistors for storing signal charges generated by photoelectric conversion, each of the bipolar pixel transistors being composed of a base connected to a scanning line, a collector connected to a voltage source and an emitter connected to a vertical signal line, a capacitor connected between the vertical signal line and a fixed potential, a switch disposed between the vertical signal line and the capacitor and a reset device for resetting the respective potentials of the capacitor and the vertical signal line.
In accordance with a third aspect of the present invention, there is provided a solid-state imaging device which is comprised of a plurality of pixel bipolar transistors for storing signal charges generated by photoelectric conversion, each of the pixel bipolar transistors being composed of a base connected to a vertical scanning line, a collector connected to a voltage source and an emitter connected to a vertical signal line, a capacitor connected between the vertical signal line and a fixed potential and a reset device for resetting a potential of the capacitor to set a reset potential which is shallower than that obtained in a base of the pixel bipolar transistor when no light is incident on the pixel bipolar transistor, a difference between the reset potential and the base potential being set so as to fall within 2.0V.